During the last several decades, memory technology has progressed dramatically. The density of commercial memory devices, taking Dynamic Random Access Memory (DRAM) as a convenient example, has increased from 1 Kbit to 64 Mbits per chip, a factor of 64,000. Unfortunately, memory device performance has not kept pace with increasing memory device densities. In fact memory device access times during the same time period has only improved by about a factor of 5. By comparison, during the past twenty years, microprocessor performance has increased by several orders of magnitude. This growing disparity between the speed of microprocessors and that of memory devices has forced memory system designers to create a variety of complicated and expensive hierarchical memory techniques, such as Static Random Access Memory (SRAM) caches and parallel DRAM arrays. Further, now that computer system users increasingly demand high performance graphics and other memory hungry applications, memory systems often rely on expensive frame buffers to provide the necessary data bandwidth. Increasing memory device densities satisfy the overall quantitative demand for data with fewer chips, but the problem of effectively accessing data at peak microprocessor speeds remains.
Massively parallel DRAM arrays having relatively wide buses have been a typical response to the demand for more data bandwidth at higher access speeds. FIGS. 1 and 2 illustrate generic, conventional memory systems having a memory controller 10 connected to a number of memory devices 12 via a wide bus structure. In FIG. 1, each memory device 12 is connected to memory controller 10 via sixteen (16) dedicated bus lines. (Not all bus lines are individually shown for the sake of clarity). Assuming four memory devices in the system of FIG. 1, the data bus is 64 lines wide. This structure allows the memory controller to directly send and receive data from a specific memory device without interference from any other memory device. However, each data bit so sent and received requires the addition of another data line to the bus.
In the memory system shown in FIG. 2, a single 64-bit line, data bus is shared by four 64-bit memory devices. In the example shown in FIG. 1, accessing four 64-bit memory devices would require a 256 line wide data bus. Thus, the structure of the memory system shown in FIG. 2 represents an advance over that of FIG. 1. However, the reduction in relative data bus width comes with some additional overhead. In the memory system of FIG. 2, each memory device receives an individual set of control signals 14 from memory controller 10. These separately transmitted signals are required to regulate memory device access to the common data bus lines.
As can be seen from the foregoing examples, conventional memory systems use a large number of data lines, or a relatively wide bus. The term “line(s)” is used to describe the physical means by which data bits are electronically communicated from one point to another in a system. A line may take the form, alone or in combination, of a printed circuit board (PCB) strip, metal contact, pin and/or via, microstrip, semiconductor channel, etc. A line may be single or may be associated with a bus. A “bus” is a collection, fixed or variable, of lines, and may also be used to describe the drivers, latches, buffers, and other elements associated with an operative collection of lines. In the description of the invention which follows, a bus may communicate control information, address information, and/or data. In the foregoing examples of conventional memory systems, the bus was assumed to transmit data only. Address and control information is separately transmitted by additional lines or buses.
Such massively parallel, or wide buses, are required in conventional memory systems due to the slow access speed of the individual memory devices. Wide buses have long been associated with implementation and performance problems, such as excessive power consumption, slow speed, loss of expandability and design flexibility, etc. As a result, bus multiplexing of control, address and/or data information has become commonplace. Multiplexing, in any of its varied forms, effectively “time-shares” a bus between a number of devices.
Multiplexing allows reduction in bus size. It also greatly increases system complexity. Such complexity often results in increased memory system rigidity. That is, once implemented in all its complexity, the integration of a new function into the bus-multiplexing memory system becomes extremely difficult. In particular, memory system designers continue to face enormous challenges in increasing data throughput while minimizing system complexity, and maintaining system reliability.